Recently, with a development of digital technology, a demand for a higher-speed operation, lower power consumption, and downsizing of an A/D conversion circuit that converts an analog signal to a digital signal has more and more increased. As an A/D conversion circuit that implements high-speed and low-power A/D conversion, there is known a circuit configuration where a plurality of stages of one-bit flash-type A/D converters (including a small number of amplifier circuits, comparators, and selectors) are connected to obtain desired accuracy and resolution (number of bits)(refer to Non-patent Document 1, for example).
FIG. 9 is a diagram for explaining the related art described in Non-patent Document 1. FIG. 9 illustrates an overall configuration (represented by first three stages) of a circuit where a plurality of stages (N stages) of one-bit A/D converters 10′, each including differential amplifier circuits 11 to 14, a comparator 14, and a selector 15, are cascade-connected. FIG. 9 is prepared by the inventor of the present invention in order to explain the related art.
FIG. 10 is a diagram for explaining a configuration of the one-bit A/D converter 10′ (of each stage having the same configuration) in FIG. 9. FIG. 10 illustrates the configuration of a first stage.
FIGS. 11A and 11B are graphs for explaining direct-current (DC) transfer characteristics (input-output characteristics of input voltage versus output voltages) of an output Va of the amplifier circuit 11, an output Vb of the amplifier circuit 12, and an output Vc of the amplifier circuit 13 of the one-bit A/D converter 10′ in FIG. 10 with respect to the input voltage, and an output ADOUT of the comparator. FIG. 11C is a graph explaining DC transfer characteristics of outputs Voa and Vob of the selector 15. In FIGS. 11A and 11C, a horizontal axis (X axis) indicates an input voltage, and a vertical axis (Y axis) indicates an output voltage. FIGS. 11D and 11E are graphs showing selection states of the selector 15. FIGS. 10 and 11A, 11B, 11C, 11D, and 11E are all prepared by the inventor of the present invention in order to explain the related art.
Referring to FIG. 10, a first preamplifier circuit 21 that differentially receives an input signal voltage Vin and a reference voltage A (voltage at a tap A of a ladder resistor) for differential amplification and a second preamplifier circuit 22 that differentially receives the input signal voltage Vin and a reference voltage B (voltage at a tap B of the ladder resistor) for differential amplification are disposed in an immediately preceding stage of the A/D converter 10′ in the first stage.
The one-bit A/D converter 10′ in the first stage includes:                a first amplifier circuit 11 that differentially receives and differentially amplifies a differential output Via of the first preamplifier circuit 21;        a second amplifier circuit 12 that differentially receives and differentially amplifies a differential output Vib of the second preamplifier circuit 22;        a third amplifier circuit 13 (also referred to as an “interpolating amplifier circuit”) that differentially receives a non-inverting input of the first amplifier circuit 11 and an inverting input of the second amplifier circuit 12, and differentially amplifies the received signals;        a comparator 14 that differentially receives a differential output Vc of the third amplifier circuit 13 to output a result of comparison as a binary logic signal (digital signal); and        a selector 15 that respectively receives three differential outputs of the differential output Va of the first amplifier circuit 11, the differential output Vb of the second amplifier circuit 12, and the differential output Vc of the third amplifier circuit 13 at first to third differential input terminals thereof, and then selects and outputs two (e.g., the outputs Vc and Vb or the outputs Va and Vc as shown in FIGS. 11D and 11E) of the three differential outputs (Va, Vb, Vc) at first and second differential output terminals thereof.        
The first preamplifier circuit 21 differentially receives the input signal voltage Vin=VCMA+(Vin−VA)/2 at a non-inverting input terminal thereof and a voltage VA=VCMA−(Vin−VA)/2 at an inverting input terminal thereof (input terminal with a circle), where VCMA is a midpoint voltage between the input voltage Vin and the voltage VA at the tap A and is given by VCMA=(Vin+VA)/2. The first preamplifier circuit 21 differentially outputs a voltage VCMAO+Via/2 (where VCMAO is a midpoint voltage between differential outputs) at a non-inverting output terminal thereof and a voltage VCMAO−Via/2 at an inverting output terminal thereof (output terminal with a circle). A difference voltage between these differential outputs is given as follows: (VCMAO+Via/2)−(VCMAO−Via/2)=Via.
The second preamplifier circuit 22 differentially receives the input voltage Vin=VCMB+(Vin−VB)/2 at a non-inverting input terminal thereof and a voltage VB=VCMB−(Vin−VB)/2 at an inverting input terminal thereof (input terminal with a circle), where VCMB indicates a midpoint voltage between the input voltage Vin and the voltage VB at the tap B and is given by VCMB=(Vin+VB)/2. Then, the first preamplifier circuit 21 differentially outputs from a non-inverting output terminal thereof a voltage VCMBO+Vib/2(where VCMBO indicates a midpoint voltage between differential outputs) and outputs from an inverting output terminal (output terminal with a circle) a voltage VCMBo−Vib/2. A difference voltage between these differential outputs is given as follows: (VCMBo+Vib/2)−(VCMBo−Vib/2)=Vib. The first and second preamplifier circuits 21 and 22 have the same configuration.
The first amplifier circuit 11 differentially receives the differential signal Via (VCMI1+Va/2, VCMI1−Va/2) from the first preamplifier circuit 21, and differentially amplifies the received signal to output first differential signals VCM1O+Va/2, VCM1O−Va/2. A difference voltage between the first differential signals is given as follow: (VCM1O+Va/2)−(VCM1O−Va/2)=Va. VCM1I and VCM1O respectively are midpoint voltages (common-mode voltages) of the differential input signals and the differential output signals of the first amplifier circuit 11.
The second amplifier circuit 12 differentially receives the differential signal Vib (differential signals: VCM2I+Vib/2, VCM2I−Vib/2) from the second preamplifier circuit 22, and differentially amplifies the received signal to output second differential signals VCM2O+Vb/2, VCM2O−Vb/2 (a differential voltage Vb). A difference voltage between the second differential signals is given as follows: (VCM2O+Vb/2)−(VCM2O−Vb/2)=Vb. VCM2I and VCM2O respectively are midpoint voltages (common-mode voltages) of the differential input signals and the differential output signals of the second amplifier circuit 12.
The third amplifier circuit 13 differentially receives the non-inverting output VCM1O+Va/2 from the first amplifier circuit 11 and the inverting output VCM2O−Vb/2 from the second amplifier circuit 12 (a differential voltage: (Va+Vb)/2, and differentially amplifies received signals to output differential signals VCM3O+Va/2 and VCM3O−Vb/2. A difference voltage between the differential outputs is given as follows: (VCM3O+Va/2)−(VCM3O−Vb/2)=(Va+Vb)/2, where VCM3O is a midpoint voltage (common-mode voltage) of the differential output signals of the third amplifier circuit 13. Since the third amplifier circuit 13 outputs an intermediate voltage obtained by interpolating the voltages Va and Vb (internal division with an internal division ratio of 1:1), the third amplifier circuit 13 is referred to as the “interpolating amplifier circuit”. In the example shown in FIG. 10, the first amplifier circuit 11, the second amplifier circuit 12, and the third amplifier circuit 13 have the same configuration to one another.
FIG. 10 shows the one-bit A/D converter 10′ in the first stage. The first amplifier circuit 11 and the second amplifier circuit 12 of each one-bit A/D converter 10′ in each stage after a second stage differentially receive a first differential output Voa from first differential output terminals and a second differential output Vob from second differential output terminals in the selector 15 of the one-bit A/D converter 10′ in the immediately preceding stage, respectively, as shown in FIG. 9.
The comparator 14 differentially receives the differential signals from the third amplifier circuit 13 to output a High/Low level as an output ADOUT, which is a logic value signal, according to a polarity of the differential voltage Vc between the differential signals from the third amplifier circuit 13.
When the output ADOUT of the comparator 14 is Low, the selector 15 selects the differential output Vc of the third amplifier circuit 13 and the differential output Vb of the second amplifier circuit 12, and respectively outputs the differential outputs Vc and the differential outputs Vb as the first differential output Voa and the second differential output Vob (as shown in FIG. 11D).
When the output ADOUT of the comparator 14 is High, the selector 15 selects the differential output Va of the first amplifier circuit 11 and the differential output Vc of the third amplifier circuit 13, and respectively outputs the differential outputs Va and Vc as the first differential output Voa and the second differential output Vob (as shown in FIG. 11E).
As shown in FIG. 11A, the first differential output voltage Va of the first amplifier circuit 11 and the second differential output voltage Vb of the second amplifier circuit 12 have DC transfer characteristics (indicated by a dashed-dotted line and a broken line) respectively having different zero-cross points A and B. The differential output voltage Vc of the third amplifier circuit 13 has a DC transfer characteristic (indicated by a solid line) having a zero-cross point at a midpoint C between the points A and B. As shown in FIG. 11A, the third amplifier circuit 13 outputs an interpolated value between the voltages Va and Vb (intermediate value Vc=Va+Vb)/2 in this example), as the voltage Vc.
In the one-bit A/D converter 10′, the polarity of the differential output voltage Vc of the third amplifier circuit 13 is decided by the comparator 14, and an input voltage to the A/D converter 10′ is distinguished between two levels (segments) ([A−C], [C−B]) using the midpoint C as a boundary.
As described before, the selector 15 selects the differential output voltages Vc and Vb or Va and Vc among the three differential output voltages Va, Vb, and Vc to output as the first differential output Voa and the second differential output Vob, according to a value of the output ADOUT of the comparator 14. The DC transfer characteristics (direct-current transfer characteristics of output voltages with respect to input voltage) as shown in FIG. 11C are thereby obtained.
Referring to FIG. 11C, the first differential output Voa of the selector 15 (a dashed-dotted line) is the output Vc in FIG. 11A when the input voltage is less than or equal to a voltage at the midpoint C of a segment between the points A and B, and is zero when the input voltage is the voltage at the midpoint C (zero-cross point). When the input voltage is larger than the voltage at the point C, the output Vc in FIG. 11A is positive, and the output ADOUT is High. Thus, the output Va in FIG. 11A is output as the first differential output Voa of the selector 15. The first differential output Voa of the selector 15 changes to a negative value from zero at the point C, and becomes discontinuous at the point C. The second differential output Vob of the selector 15 (a broken line) is the output Vb in FIG. 11A when the input voltage has a voltage value less than or equal to the voltage at the midpoint C of the segment between the points A and B. When the input voltage becomes larger than the voltage at the point C, the output Vc in FIG. 11A becomes positive, and the output ADOUT goes High. For this reason, the output Vc in FIG. 11A is output as the second differential output Vob of the selector 15, and the output Vob changes from a positive value to zero at the point C, and becomes discontinuous at the point C.
By cascade-connecting N stages of the one-bit A/D converters as shown in FIG. 9, using the one-bit A/D converters 10′ described with reference to FIGS. 10 and 11 as a unit circuit, an N-bit A/D conversion circuit is formed. Then, differential output signals Van, Vbn, and Vcn (n=1, 2, 3, . . . , N) and an N-bit digital signal ADOUT n (n=1, 2, 3, . . . N) as shown in FIGS. 12B to 12G can be obtained.
FIGS. 12B and 12C are graphs illustrating DC transfer characteristics (relationships between an input voltage and each of an output voltage Va1 of the amplifier circuit 11, an output voltage Vb1 of the amplifier circuit 12, and an output voltage Vc1 of the amplifier circuit 13) in the one-bit A/D converter 10′ in a first stage in FIG. 12A and a signal waveform of an output ADOUT1 of the comparator 14 of the one-bit A/D converter 10′ in the first stage. FIGS. 12B and 12C correspond to FIGS. 11A and 11B. The output ADOUT1 of the comparator 14 that receives the output voltage Vc1 is Low when Vc1<=0, and is High when Vc1>0. When the input voltage becomes less than or equal to a voltage at a point C (Vc1<=0), the output ADOUT1 goes Low. When the input voltage becomes greater than or equal to the voltage at the point C (Vc1>=0), the output ADOUT1 is High.
FIGS. 12D and 12E are graphs illustrating DC transfer characteristics (of output voltages Va2, Vb2, and Vc2 with respect to the input voltage) in the one-bit A/D converter 10′ in FIG. 12A in a second stage and a signal waveform of an output ADOUT2 of the comparator 14 of the one-bit A/D converter 10′ in the second stage. FIG. 12D corresponds to FIG. 11C. The output ADOUT2 of the comparator 14 that receives the output voltage Vc2 is Low when Vc2≦0, and is High when Vc2>0. When the input voltage becomes less than or equal to a voltage at a midpoint E between the points B and C, the output ADOUT2 is Low. When the input voltage is in a range between the point C and the point E, the output ADOUT2 is High. The output ADOUT2 is Low when the input voltage is in a range between the point C and a midpoint D of the point C and the point A. When the input voltage is greater than or equal to a voltage at the point D, the output ADOUT2 is High.
FIGS. 12F and 12G are graphs illustrating DC transfer characteristics (output voltages Va3, Vb3, and Vc3 with respect to the input voltage) in the one-bit A/D converter 10′ in FIG. 12A in a third stage and a signal waveform of an output ADOUT3 of the comparator 14 of the one-bit A/D converter 10′ in the third stage. The output ADOUT3 of the comparator 14 that receives the output voltage Vc3 is Low when Vc3<=0, and is High when Vc3>0. When the input voltage is less than or equal to a voltage at the midpoint between points B and E, the output AOUT 3 is Low. When the input voltage is in a range between the point E and the midpoint between the point B and the point E, the output ADOUT3 is High. When the input voltage is in a range between the point E and the midpoint between the points E and C, the output ADOUT3 is Low. When the input voltage is in a range between the point C and the midpoint between the points E and C, the output ADOUT3 is High. When the input voltage is in a range between the point C and the midpoint between the point C and the point D (midpoint between the points A and C), the output ADOUT3 is Low. When the input voltage is in a range between the point D and the midpoint between the points C and D, the output ADOUT3 is High. When the input voltage is in a range between the point D and the midpoint between the point A and the point D, the output ADOUT3 is Low. When the input voltage is equal to or higher than a voltage at the midpoint between the points D and A, the output ADOUT3 is High.
As shown in FIGS. 12B, 12D, and 12F, the one-bit A/D converter 10′ in each stage has a DC transfer characteristic of an output differential voltage Vcn (n=1, 2, 3, . . . N) such that zero-cross points of the DC transfer characteristic equally divides a segment A−B by 2n (n powers of 2).
As shown in FIG. 12B, for example, the output differential voltage Vc1 has one zero-cross point at the point C and equally divides the input voltage segment A−B by two. The output differential voltage Vc2 has three zero-cross points of the points E, C, and D, and equally divides the input voltage segment A−B by 22=4 as shown in FIG. 12D. The output differential voltage Vc3 has a total of seven zero-cross points which are the midpoint between the points B and E, the point E, the midpoint between the points E and C, the point C, the midpoint between the points C and D, the point D, and the midpoint between the points D and A, and these zero-cross points equally divide the input voltage segment A−B by 23=8.
When the output ADOUTn (n=1, 2, . . . , N) being the output of the comparator 14 of the one-bit A/D converter 10′ in each stage is set to constitute the N-bit digital signal, a N-bit binary code as shown in FIG. 13(A) to (D) is obtained. FIG. 13(A) to (D) show a relationship between each of outputs ADOUT1 to ADOUT3 and the input voltage. The output ADOUT1 corresponds to an MSB (Most Significant Bit), and an output ADOUTN corresponds to an LSB (Least Significant Bit).
The following describes a code of the outputs ADOUT1, ADOUT2, and ADOUT3 of a three-bit digital signal, in case N is set to 3 and the input voltage segment A−B is equally divided by 23=8. It is assumed that D=(A+C)/2 and E=(B+C)/2.    (1) In case an input voltage Vin is greater than or equal to a voltage at a point (A+D)/2, (ADOUT1, ADOUT2, ADOUT3)=(1, 1, 1);    (2) In case the input voltage Vin is in a voltage segment [D, (A+D)/2], (ADOUT1, ADOUT2, ADOUT3)=(1, 1, 0);    (3) In case the input voltage Vin is in a voltage segment [(C+D)/2, D], (ADOUT1, ADOUT2, ADOUT3)=(1, 0, 1);    (4) In case the input voltage Vin is in a voltage segment [C, (C+D)/2], (ADOUT1, ADOUT2, ADOUT3)=(1, 0, 0);    (5) In case the input voltage Vin is in a voltage segment [(E+C)/2, C], (ADOUT1, ADOUT2, ADOUT3)=(0, 1, 1);    (6) In case the input voltage Vin is in a voltage segment [E, (E+C)/2], (ADOUT1, ADOUT2, ADOUT3)=(0, 1, 0);    (7) In case the input voltage Vin is in a voltage segment [(B+E)/2, E], (ADOUT1, ADOUT2, ADOUT3)=(0, 0, 1);    (8) In case the input voltage Vin is less than or equal to a voltage at a point (B+E)/2, (ADOUT1, ADOUT2, ADOUT3)=(0, 0, 0).
By (cascade) connecting a plurality (N) of stages of the one-bit A/D converters 10′ in cascade as described above,
An N-bit A/D conversion circuit can be configured where the output ADOUT1 of the one-bit A/D converter 10′ in a first stage is set to the MSB and the output ADOUTN of the one-bit A/D converter 10′ in an Nth stage is set to the LSB.
The following describes Patent Documents 1 and 2 found by prior art document search conducted by the applicant of the present invention. Patent Document 1 discloses an A/D converter where a plurality of stages of pipe line cells are cascade-connected. Each pipeline cell includes a sample and hold circuit that samples and holds a signal in an immediately preceding stage, a comparator that compares an output of the sample and hold circuit with a comparison reference signal, and a subtractor that subtracts a subtraction signal from the output of the sample and hold circuit. Patent Document 2 discloses an A/D converter with a folding architecture where an input signal is folded by folding stages, a folded signal obtained by the folding has four upward edges and four downward edges, and an amplitude range of the folded signal is reduced to one eighth of an amplitude range of the input signal. While 256 comparators are necessary for a flash-type A/D converter, the number of comparators necessary for the A/D converter with the folding architecture is reduced to 32. Patent Document 1 and 2 do not disclose or suggest recognition of a problem of the A/D conversion circuit described with reference to FIGS. 9 to 12 (which will be described below) and means for solving the problem.    [Patent Document 1] JP Patent Kokai Publication No. JP-A-08-195678    [Patent Document 2] JP Patent Kokai Publication No. JP-A-09-502856    [Non-patent Document 1] Yun-Ti Wang and Behzad Razavi, “An 8-Bit 150-MHz CMOS A/D Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000